FMC_Connector_FPGA Project Status (12/21/2017 - 10:56:26)
Project File: Transceiver_FMCOMMS4.xise Parser Errors: No Errors
Module Name: FMC_Connector_FPGA Implementation State: Programming File Generated
Target Device: xc6slx9-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
93 Warnings (0 new)
Design Goal: Timing Performance
  • Routing Results:
All Signals Completely Routed
Design Strategy: Performance with IOB Packing
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
103351  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 2,106 11,440 18%  
    Number used as Flip Flops 2,106      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 1,787 5,720 31%  
    Number used as logic 1,587 5,720 27%  
        Number using O6 output only 954      
        Number using O5 output only 110      
        Number using O5 and O6 523      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 200      
        Number with same-slice register load 195      
        Number with same-slice carry load 5      
        Number with other load 0      
Number of occupied Slices 727 1,430 50%  
Number of MUXCYs used 444 2,860 15%  
Number of LUT Flip Flop pairs used 2,195      
    Number with an unused Flip Flop 525 2,195 23%  
    Number with an unused LUT 408 2,195 18%  
    Number of fully used LUT-FF pairs 1,262 2,195 57%  
    Number of unique control sets 151      
    Number of slice register sites lost
        to control set restrictions
534 11,440 4%  
Number of bonded IOBs 128 200 64%  
    Number of LOCed IOBs 128 128 100%  
    IOB Flip Flops 76      
Number of RAMB16BWERs 22 32 68%  
Number of RAMB8BWERs 7 64 10%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 5 16 31%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 31 200 15%  
    Number used as ILOGIC2s 31      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 45 200 22%  
    Number used as OLOGIC2s 45      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.46      
 
Performance Summary [-]
Final Timing Score: 103351 (Setup: 96787, Hold: 6564, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 21. Dez 10:54:43 2017034 Warnings (0 new)124 Infos (0 new)
Translation ReportCurrentDo 21. Dez 10:54:49 201708 Warnings (0 new)2 Infos (0 new)
Map ReportCurrentDo 21. Dez 10:55:13 2017024 Warnings (0 new)11 Infos (0 new)
Place and Route ReportCurrentDo 21. Dez 10:56:06 2017023 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentDo 21. Dez 10:56:11 201703 Warnings (0 new)3 Infos (0 new)
Bitgen ReportCurrentDo 21. Dez 10:56:21 201701 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentDo 21. Dez 10:56:21 2017
WebTalk Log FileCurrentDo 21. Dez 10:56:26 2017

Date Generated: 01/25/2018 - 10:07:58