User_FPGA Project Status (10/09/2017 - 11:25:49)
Project File: UART_Demo.xise Parser Errors: No Errors
Module Name: User_FPGA Implementation State: Programming File Generated
Target Device: xc6slx75-2fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
99 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 166 93,296 1%  
    Number used as Flip Flops 166      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 128 46,648 1%  
    Number used as logic 111 46,648 1%  
        Number using O6 output only 83      
        Number using O5 output only 0      
        Number using O5 and O6 28      
        Number used as ROM 0      
    Number used as Memory 0 11,072 0%  
    Number used exclusively as route-thrus 17      
        Number with same-slice register load 17      
        Number with same-slice carry load 0      
        Number with other load 0      
Number of occupied Slices 67 11,662 1%  
Number of MUXCYs used 0 23,324 0%  
Number of LUT Flip Flop pairs used 177      
    Number with an unused Flip Flop 40 177 22%  
    Number with an unused LUT 49 177 27%  
    Number of fully used LUT-FF pairs 88 177 49%  
    Number of unique control sets 24      
    Number of slice register sites lost
        to control set restrictions
90 93,296 1%  
Number of bonded IOBs 148 280 52%  
    Number of LOCed IOBs 148 148 100%  
Number of RAMB16BWERs 0 172 0%  
Number of RAMB8BWERs 2 344 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 12 0%  
Number of ILOGIC2/ISERDES2s 0 442 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 442 0%  
Number of OLOGIC2/OSERDES2s 0 442 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 384 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 132 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 4 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 6 16%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.97      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo 9. Okt 11:24:58 2017017 Warnings (0 new)13 Infos (0 new)
Translation ReportCurrentMo 9. Okt 11:25:01 2017014 Warnings (0 new)1 Info (0 new)
Map ReportCurrentMo 9. Okt 11:25:14 201701 Warning (0 new)9 Infos (0 new)
Place and Route ReportCurrentMo 9. Okt 11:25:26 2017066 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentMo 9. Okt 11:25:32 2017003 Infos (0 new)
Bitgen ReportCurrentMo 9. Okt 11:25:44 201701 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentMo 9. Okt 11:25:44 2017
WebTalk Log FileCurrentMo 9. Okt 11:25:49 2017

Date Generated: 10/09/2017 - 11:25:49