Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT Target Device: xc6slx75
Project ID (random number) 1e73c88c041a47a094c05a6645881fb0.3093E2FB57524CABA4A40F43D4DC1F16.2 Target Package: fgg484
Registration ID 176250593_0_0_453 Target Speed: -2
Date Generated 2017-10-09T11:25:44 Tool Flow ISE
 
User Environment
OS Name Microsoft , 32-bit OS Release major release (build 9200)
CPU Name Intel(R) Xeon(R) CPU E3-1275 v3 @ 3.50GHz CPU Speed 3492 MHz
OS Name Microsoft , 32-bit OS Release major release (build 9200)
CPU Name Intel(R) Xeon(R) CPU E3-1275 v3 @ 3.50GHz CPU Speed 3492 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 9-bit adder=1
Comparators=5
  • 8-bit comparator greater=4
  • 9-bit comparator greater=1
Counters=2
  • 4-bit up counter=2
FSMs=2 Multiplexers=10
  • 1-bit 2-to-1 multiplexer=7
  • 1-bit 8-to-1 multiplexer=1
  • 9-bit 2-to-1 multiplexer=2
Registers=48
  • Flip-Flops=48
MiscellaneousStatistics
  • AGG_BONDED_IO=148
  • AGG_IO=148
  • AGG_LOCED_IO=148
  • AGG_SLICE=67
  • NUM_BONDED_IOB=148
  • NUM_BSFULL=88
  • NUM_BSLUTONLY=40
  • NUM_BSREGONLY=49
  • NUM_BSUSED=177
  • NUM_BUFG=1
  • NUM_BUFIO2=1
  • NUM_LOCED_IOB=148
  • NUM_LOGIC_O5ANDO6=28
  • NUM_LOGIC_O6ONLY=83
  • NUM_LUT_RT_DRIVES_FLOP=17
  • NUM_LUT_RT_EXO5=17
  • NUM_PLL_ADV=1
  • NUM_RAMB8BWER=2
  • NUM_SLICEL=5
  • NUM_SLICEX=62
  • NUM_SLICE_CONTROLSET=24
  • NUM_SLICE_CYINIT=156
  • NUM_SLICE_F7MUX=5
  • NUM_SLICE_FF=166
  • NUM_SLICE_UNUSEDCTRL=5
  • NUM_UNUSABLE_FF_BELS=90
  • Xilinx Core fifo_generator_v9_3, Xilinx CORE Generator 14.7=2
NetStatistics
  • NumNets_Active=464
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=6
  • NumNodesOfType_Active_BOUNCEIN=39
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_BUFIOINP=1
  • NumNodesOfType_Active_CLKPIN=64
  • NumNodesOfType_Active_CLKPINFEED=6
  • NumNodesOfType_Active_CNTRLPIN=83
  • NumNodesOfType_Active_DOUBLE=193
  • NumNodesOfType_Active_GENERIC=5
  • NumNodesOfType_Active_GLOBAL=31
  • NumNodesOfType_Active_INPUT=59
  • NumNodesOfType_Active_IOBIN2OUT=2
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_LUTINPUT=553
  • NumNodesOfType_Active_OUTBOUND=266
  • NumNodesOfType_Active_OUTPUT=254
  • NumNodesOfType_Active_PADINPUT=2
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=202
  • NumNodesOfType_Active_PINFEED=725
  • NumNodesOfType_Active_QUAD=65
  • NumNodesOfType_Active_REGINPUT=73
  • NumNodesOfType_Active_SINGLE=385
  • NumNodesOfType_Gnd_BOUNCEIN=20
  • NumNodesOfType_Gnd_CNTRLPIN=1
  • NumNodesOfType_Gnd_DOUBLE=27
  • NumNodesOfType_Gnd_GENERIC=76
  • NumNodesOfType_Gnd_HGNDOUT=12
  • NumNodesOfType_Gnd_INPUT=90
  • NumNodesOfType_Gnd_IOBIN2OUT=76
  • NumNodesOfType_Gnd_IOBOUTPUT=76
  • NumNodesOfType_Gnd_OUTBOUND=27
  • NumNodesOfType_Gnd_OUTPUT=31
  • NumNodesOfType_Gnd_PADINPUT=76
  • NumNodesOfType_Gnd_PINBOUNCE=43
  • NumNodesOfType_Gnd_PINFEED=156
  • NumNodesOfType_Gnd_REGINPUT=8
  • NumNodesOfType_Gnd_SINGLE=67
  • NumNodesOfType_Vcc_GENERIC=4
  • NumNodesOfType_Vcc_HVCCOUT=24
  • NumNodesOfType_Vcc_IOBIN2OUT=4
  • NumNodesOfType_Vcc_IOBOUTPUT=4
  • NumNodesOfType_Vcc_LUTINPUT=28
  • NumNodesOfType_Vcc_PADINPUT=4
  • NumNodesOfType_Vcc_PINFEED=32
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=73
  • IOB-IOBS=75
  • SLICEL-SLICEM=1
  • SLICEX-SLICEL=13
  • SLICEX-SLICEM=13
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • BUFIO2=1
  • BUFIO2_BUFIO2=1
  • FF_SR=31
  • IOB=148
  • IOB_IMUX=66
  • IOB_INBUF=66
  • IOB_OUTBUF=81
  • LUT5=45
  • LUT6=111
  • NULLMUX=1
  • PAD=148
  • PLL_ADV=1
  • PLL_ADV_PLL_ADV=1
  • RAMB8BWER=2
  • RAMB8BWER_RAMB8BWER=2
  • REG_SR=135
  • SELMUX2_1=5
  • SLICEL=5
  • SLICEX=62
 
Configuration Data
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
FF_SR
  • CK=[CK:31] [CK_INV:0]
  • SRINIT=[SRINIT0:31]
  • SYNC_ATTR=[ASYNC:31]
IOB_INBUF
  • DIFF_TERM=[FALSE:1]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:81]
  • SLEW=[SLOW:81]
  • SUSPEND=[3STATE:81]
PLL_ADV
  • RST=[RST:1] [RST_INV:0]
PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLK_FEEDBACK=[CLKFBOUT:1]
  • COMPENSATION=[INTERNAL:1]
  • PLL_ADD_LEAKAGE=[2:1]
  • PLL_AVDD_COMP_SET=[2:1]
  • PLL_CLAMP_BYPASS=[FALSE:1]
  • PLL_CLAMP_REF_SEL=[1:1]
  • PLL_CLK0MX=[0:1]
  • PLL_CLK1MX=[0:1]
  • PLL_CLK2MX=[0:1]
  • PLL_CLK3MX=[0:1]
  • PLL_CLK4MX=[0:1]
  • PLL_CLK5MX=[0:1]
  • PLL_CLKBURST_CNT=[0:1]
  • PLL_CLKBURST_ENABLE=[TRUE:1]
  • PLL_CLKCNTRL=[0:1]
  • PLL_CLKFBMX=[0:1]
  • PLL_CLKFBOUT2_EDGE=[TRUE:1]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKFBOUT_EDGE=[TRUE:1]
  • PLL_CLKFBOUT_EN=[FALSE:1]
  • PLL_CLKFBOUT_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT0_EDGE=[TRUE:1]
  • PLL_CLKOUT0_EN=[FALSE:1]
  • PLL_CLKOUT0_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT1_EDGE=[TRUE:1]
  • PLL_CLKOUT1_EN=[FALSE:1]
  • PLL_CLKOUT1_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT2_EDGE=[TRUE:1]
  • PLL_CLKOUT2_EN=[FALSE:1]
  • PLL_CLKOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT3_EDGE=[TRUE:1]
  • PLL_CLKOUT3_EN=[FALSE:1]
  • PLL_CLKOUT3_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT4_EDGE=[TRUE:1]
  • PLL_CLKOUT4_EN=[FALSE:1]
  • PLL_CLKOUT4_NOCOUNT=[TRUE:1]
  • PLL_CLKOUT5_EDGE=[TRUE:1]
  • PLL_CLKOUT5_EN=[FALSE:1]
  • PLL_CLKOUT5_NOCOUNT=[TRUE:1]
  • PLL_CLK_LOST_DETECT=[FALSE:1]
  • PLL_CP=[1:1]
  • PLL_CP_BIAS_TRIP_SHIFT=[TRUE:1]
  • PLL_CP_REPL=[1:1]
  • PLL_CP_RES=[0:1]
  • PLL_DIRECT_PATH_CNTRL=[TRUE:1]
  • PLL_DIVCLK_EDGE=[TRUE:1]
  • PLL_DIVCLK_NOCOUNT=[TRUE:1]
  • PLL_DVDD_COMP_SET=[2:1]
  • PLL_EN=[FALSE:1]
  • PLL_EN_DLY=[TRUE:1]
  • PLL_EN_LEAKAGE=[2:1]
  • PLL_EN_TCLK0=[TRUE:1]
  • PLL_EN_TCLK1=[TRUE:1]
  • PLL_EN_TCLK2=[TRUE:1]
  • PLL_EN_TCLK3=[TRUE:1]
  • PLL_EN_VCO0=[FALSE:1]
  • PLL_EN_VCO1=[FALSE:1]
  • PLL_EN_VCO2=[FALSE:1]
  • PLL_EN_VCO3=[FALSE:1]
  • PLL_EN_VCO4=[FALSE:1]
  • PLL_EN_VCO5=[FALSE:1]
  • PLL_EN_VCO6=[FALSE:1]
  • PLL_EN_VCO7=[FALSE:1]
  • PLL_EN_VCO_DIV1=[FALSE:1]
  • PLL_EN_VCO_DIV6=[TRUE:1]
  • PLL_INTFB=[0:1]
  • PLL_IO_CLKSRC=[0:1]
  • PLL_LFHF=[3:1]
  • PLL_LOCK_FB_DLY=[3:1]
  • PLL_LOCK_REF_DLY=[5:1]
  • PLL_MAN_LF_EN=[TRUE:1]
  • PLL_NBTI_EN=[TRUE:1]
  • PLL_PFD_CNTRL=[8:1]
  • PLL_PFD_DLY=[1:1]
  • PLL_PWRD_CFG=[FALSE:1]
  • PLL_REG_INPUT=[TRUE:1]
  • PLL_RES=[1:1]
  • PLL_SEL_SLIPD=[FALSE:1]
  • PLL_SKEW_CNTRL=[0:1]
  • PLL_TEST_IN_WINDOW=[FALSE:1]
  • PLL_VDD_SEL=[0:1]
  • PLL_VLFHIGH_DIS=[TRUE:1]
  • RST=[RST:1] [RST_INV:0]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:2] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:2]
  • DATA_WIDTH_A=[36:2]
  • DATA_WIDTH_B=[36:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENAWREN=[ENAWREN:2] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:2]
  • EN_RSTRAM_A=[TRUE:2]
  • EN_RSTRAM_B=[TRUE:2]
  • RAM_MODE=[SDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:2] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEAWEL0=[WEAWEL0:2] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:2]
  • WEBWEU0=[WEBWEU0:2] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:2] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[READ_FIRST:2]
  • WRITE_MODE_B=[READ_FIRST:2]
REG_SR
  • CK=[CK:135] [CK_INV:0]
  • LATCH_OR_FF=[FF:135]
  • SRINIT=[SRINIT0:108] [SRINIT1:27]
  • SYNC_ATTR=[ASYNC:135]
SLICEL
  • CLK=[CLK:4] [CLK_INV:0]
SLICEX
  • CLK=[CLK:58] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
FF_SR
  • CE=27
  • CK=31
  • D=31
  • Q=31
  • SR=24
IOB
  • DIFFI_IN=1
  • I=66
  • O=81
  • PAD=148
  • PADOUT=1
IOB_IMUX
  • I=66
  • OUT=66
IOB_INBUF
  • DIFFI_IN=1
  • OUT=66
  • PAD=66
IOB_OUTBUF
  • IN=81
  • OUT=81
LUT5
  • A1=11
  • A2=13
  • A3=26
  • A4=16
  • A5=40
  • O5=45
LUT6
  • A1=67
  • A2=79
  • A3=92
  • A4=104
  • A5=102
  • A6=107
  • O6=111
NULLMUX
  • 0=1
  • OUT=1
PAD
  • PAD=148
PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • LOCKED=1
  • RST=1
PLL_ADV_PLL_ADV
  • CLKFBIN=1
  • CLKFBOUT=1
  • CLKIN1=1
  • CLKOUT0=1
  • LOCKED=1
  • RST=1
RAMB8BWER
  • ADDRAWRADDR0=2
  • ADDRAWRADDR1=2
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR2=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR0=2
  • ADDRBRDADDR1=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR2=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI10=2
  • DIADI11=2
  • DIADI12=2
  • DIADI13=2
  • DIADI14=2
  • DIADI15=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIADI8=2
  • DIADI9=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI10=2
  • DIBDI11=2
  • DIBDI12=2
  • DIBDI13=2
  • DIBDI14=2
  • DIBDI15=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIBDI8=2
  • DIBDI9=2
  • DIPADIP0=2
  • DIPADIP1=2
  • DIPBDIP0=2
  • DIPBDIP1=2
  • DOADO0=2
  • DOADO1=2
  • DOADO8=2
  • DOADO9=2
  • DOBDO0=2
  • DOBDO1=1
  • DOBDO8=2
  • DOBDO9=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=2
  • ADDRAWRADDR1=2
  • ADDRAWRADDR10=2
  • ADDRAWRADDR11=2
  • ADDRAWRADDR12=2
  • ADDRAWRADDR2=2
  • ADDRAWRADDR3=2
  • ADDRAWRADDR4=2
  • ADDRAWRADDR5=2
  • ADDRAWRADDR6=2
  • ADDRAWRADDR7=2
  • ADDRAWRADDR8=2
  • ADDRAWRADDR9=2
  • ADDRBRDADDR0=2
  • ADDRBRDADDR1=2
  • ADDRBRDADDR10=2
  • ADDRBRDADDR11=2
  • ADDRBRDADDR12=2
  • ADDRBRDADDR2=2
  • ADDRBRDADDR3=2
  • ADDRBRDADDR4=2
  • ADDRBRDADDR5=2
  • ADDRBRDADDR6=2
  • ADDRBRDADDR7=2
  • ADDRBRDADDR8=2
  • ADDRBRDADDR9=2
  • CLKAWRCLK=2
  • CLKBRDCLK=2
  • DIADI0=2
  • DIADI1=2
  • DIADI10=2
  • DIADI11=2
  • DIADI12=2
  • DIADI13=2
  • DIADI14=2
  • DIADI15=2
  • DIADI2=2
  • DIADI3=2
  • DIADI4=2
  • DIADI5=2
  • DIADI6=2
  • DIADI7=2
  • DIADI8=2
  • DIADI9=2
  • DIBDI0=2
  • DIBDI1=2
  • DIBDI10=2
  • DIBDI11=2
  • DIBDI12=2
  • DIBDI13=2
  • DIBDI14=2
  • DIBDI15=2
  • DIBDI2=2
  • DIBDI3=2
  • DIBDI4=2
  • DIBDI5=2
  • DIBDI6=2
  • DIBDI7=2
  • DIBDI8=2
  • DIBDI9=2
  • DIPADIP0=2
  • DIPADIP1=2
  • DIPBDIP0=2
  • DIPBDIP1=2
  • DOADO0=2
  • DOADO1=2
  • DOADO8=2
  • DOADO9=2
  • DOBDO0=2
  • DOBDO1=1
  • DOBDO8=2
  • DOBDO9=2
  • ENAWREN=2
  • ENBRDEN=2
  • REGCEA=2
  • REGCEBREGCE=2
  • RSTA=2
  • RSTBRST=2
  • WEAWEL0=2
  • WEAWEL1=2
  • WEBWEU0=2
  • WEBWEU1=2
REG_SR
  • CE=81
  • CK=135
  • D=135
  • Q=135
  • SR=117
SELMUX2_1
  • 0=5
  • 1=5
  • OUT=5
  • S0=5
SLICEL
  • A=2
  • A1=2
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • AMUX=1
  • AQ=2
  • B=3
  • B1=2
  • B2=2
  • B3=3
  • B4=3
  • B5=3
  • B6=3
  • BMUX=1
  • C1=5
  • C2=5
  • C3=5
  • C4=5
  • C5=5
  • C6=5
  • CE=2
  • CLK=4
  • CMUX=3
  • CQ=2
  • CX=5
  • D1=5
  • D2=5
  • D3=5
  • D4=5
  • D5=5
  • D6=5
  • SR=4
SLICEX
  • A=11
  • A1=17
  • A2=18
  • A3=27
  • A4=33
  • A5=33
  • A6=30
  • AMUX=14
  • AQ=50
  • AX=27
  • B=12
  • B1=18
  • B2=20
  • B3=22
  • B4=22
  • B5=27
  • B6=25
  • BMUX=14
  • BQ=35
  • BX=22
  • C=8
  • C1=12
  • C2=16
  • C3=18
  • C4=18
  • C5=22
  • C6=18
  • CE=27
  • CLK=58
  • CMUX=6
  • CQ=28
  • CX=16
  • D=10
  • D1=9
  • D2=11
  • D3=15
  • D4=15
  • D5=20
  • D6=17
  • DMUX=9
  • DQ=18
  • DX=11
  • SR=50
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx9-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx75-fgg484-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx75-fgg484-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx75-fgg484-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx75-fgg484-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 403 383 0 0 0 0 0
bitgen 5170 5139 0 0 0 0 0
edif2ngd 16 16 0 0 0 0 0
map 5027 4829 0 0 0 0 0
ngc2edif 12 12 0 0 0 0 0
ngcbuild 366 366 0 0 0 0 0
ngdbuild 5189 5183 0 0 0 0 0
obngc 43 43 0 0 0 0 0
par 4819 4780 0 0 0 0 0
platgen 1 0 0 0 0 0 0
trce 4590 4590 0 0 0 0 0
xps 3 2 0 0 0 0 0
xst 6767 6679 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_r_design_panel.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2017-10-06T07:54:46
PROP_intWbtProjectID=3093E2FB57524CABA4A40F43D4DC1F16 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx75
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=fgg484
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-2
PROP_PreferredLanguage=VHDL FILE_COREGEN=1
FILE_UCF=1 FILE_VHDL=2
 
Core Statistics
Core Type=fifo_generator_v9_3
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=4 c_axi_ruser_width=1 c_axi_type=0 c_axi_wuser_width=1
c_axis_tdata_width=8 c_axis_tdest_width=4 c_axis_tid_width=8 c_axis_tkeep_width=1
c_axis_tstrb_width=1 c_axis_tuser_width=4 c_axis_type=0 c_common_clock=1
c_count_type=0 c_data_count_width=10 c_default_value=BlankString c_din_width=18
c_din_width_axis=8 c_din_width_rach=32 c_din_width_rdch=64 c_din_width_wach=32
c_din_width_wdch=64 c_din_width_wrch=2 c_dout_rst_val=0 c_dout_width=18
c_enable_rlocs=0 c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0
c_error_injection_type_rach=0 c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0
c_error_injection_type_wrch=0 c_family=spartan6 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0
c_has_axi_rd_channel=0 c_has_axi_ruser=0 c_has_axi_wr_channel=0 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=0
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=0 c_implementation_type_axis=1 c_implementation_type_rach=2 c_implementation_type_rdch=1
c_implementation_type_wach=2 c_implementation_type_wdch=1 c_implementation_type_wrch=2 c_init_wr_pntr_val=0
c_interface_type=1 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_preload_latency=1 c_preload_regs=0
c_prim_fifo_type=4kx4 c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=126 c_prog_empty_thresh_assert_val_rach=14
c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_wach=14 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=14
c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0
c_prog_empty_type_rdch=0 c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0
c_prog_full_thresh_assert_val=1022 c_prog_full_thresh_assert_val_axis=127 c_prog_full_thresh_assert_val_rach=15 c_prog_full_thresh_assert_val_rdch=1023
c_prog_full_thresh_assert_val_wach=15 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=15 c_prog_full_thresh_negate_val=1021
c_prog_full_type=0 c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_wach=0 c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0
c_rd_data_count_width=10 c_rd_depth=1024 c_rd_freq=1 c_rd_pntr_width=10
c_rdch_type=0 c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_wach=0 c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0
c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0 c_wr_data_count_width=10
c_wr_depth=1024 c_wr_depth_axis=128 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_freq=1
c_wr_pntr_width=10 c_wr_pntr_width_axis=7 c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10
c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4 c_wr_response_latency=1
c_wrch_type=0
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFGDS=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=8 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_FDCE=91
NGDBUILD_NUM_FDE=18 NGDBUILD_NUM_FDP=27 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFGDS=1 NGDBUILD_NUM_INV=11 NGDBUILD_NUM_LUT2=22 NGDBUILD_NUM_LUT3=12
NGDBUILD_NUM_LUT4=23 NGDBUILD_NUM_LUT5=17 NGDBUILD_NUM_LUT6=58 NGDBUILD_NUM_MUXF7=5
NGDBUILD_NUM_OBUF=81 NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_VCC=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=8 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_FDCE=91
NGDBUILD_NUM_FDE=18 NGDBUILD_NUM_FDP=27 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=65
NGDBUILD_NUM_IBUFGDS=1 NGDBUILD_NUM_INV=11 NGDBUILD_NUM_LUT2=22 NGDBUILD_NUM_LUT3=12
NGDBUILD_NUM_LUT4=23 NGDBUILD_NUM_LUT5=17 NGDBUILD_NUM_LUT6=58 NGDBUILD_NUM_MUXF7=5
NGDBUILD_NUM_OBUF=81 NGDBUILD_NUM_PLL_ADV=1 NGDBUILD_NUM_RAMB8BWER=2 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx75-2-fgg484
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5